Cypress Semiconductor /psoc63 /BLE /BLESS /DDFT_CONFIG

Enables the DDFT output from BLESS 1: DDFT is enabled 0: DDFT is disabled

Enables the DDFT inputs from CYBLERD55 chip 1: DDFT inputs are enabled 0: DDFT inputs are disabled

dbg_mux_pin1 selection, combine with BLERD and BLESS 5’h00 blerd_ddft_out[0] 5’h01 rcb_tx_fifo_empty 5’h02 hv_ldo_lv_detect_raw 5’h03 dbus_rx_en 5’h04 1’b0 5’h05 clk_switch_to_sysclk 5’h06 ll_clk_en_sync 5’h07 dsm_entry_stat 5’h08 proc_tx_en 5’h09 rssi_read_start 5’h0A tx_2mbps 5’h0B rcb_bus_busy 5’h0C hv_ldo_en_mt (act_stdbyb) 5’h0D ll_eco_clk_en 5’h0E blerd_reset_assert 5’h0F hv_ldo_byp_n 5’h10 hv_ldo_lv_detect_mt 5’h11 enable_ldo 5’h12 enable_ldo_dly 5’h13 bless_rcb_le_out 5’h14 bless_rcb_clk_out 5’h15 bless_dig_ldo_on_out 5’h16 bless_act_ldo_en_out 5’h17 bless_clk_en_out 5’h18 bless_buck_en_out 5’h19 bless_ret_switch_hv_out 5’h1A efuse_rw_out 5’h1B efuse_avdd_out 5’h1C efuse_config_efuse_mode 5’h1D bless_dbus_tx_en_pad 5’h1E bless_bpktctl_rd 5’h1F 1’b0

dbg_mux_pin2 selection, combine with BLERD and BLESS 5’h00 blerd_ddft_out[1] 5’h01 rcb_rx_fifo_empty 5’h02 ll_decode_rxdata 5’h03 dbus_tx_en 5’h04 fw_clk_en 5’h05 interrupt_ll_n 5’h06 llh_st_sm 5’h07 llh_st_dsm 5’h08 proc_rx_en 5’h09 rssi_rx_done 5’h0A rx_2mbps 5’h0B rcb_ll_ctrl 5’h0C hv_ldo_byp_n 5’h0D reset_deassert 5’h0E rcb_intr 5’h0F rcb_ll_intr 5’h10 hv_ldo_en_mt (act_stdbyb) 5’h11 hv_ldo_lv_detect_raw 5’h12 bless_rcb_data_in 5’h13 bless_xtal_en_out 5’h14 bless_isolate_n_out 5’h15 bless_reset_n_out 5’h16 bless_ret_ldo_ol_hv_out 5’h17 bless_txd_rxd_out 5’h18 tx_rx_ctrl_sel 5’h19 bless_bpktctl_cy 5’h1A efuse_cs_out 5’h1B efuse_pgm_out 5’h1C efuse_sclk_out 5’h1D hv_ldo_lv_detect_mt 5’h1E enable_ldo 5’h1F enable_ldo_dly